This invention relates to the transfer of data between a microprocessor and a peripheral unit connected thereto and, more particularly, to such a transfer when the microprocessor operates as a sixteen bit microprocessor and the peripheral unit operates in an eight bit mode.
Typically, a microprocessor is connected to a plurality of peripheral units via an address bus and a data bus. The peripheral units may be memory devices, display units, printers, or the like. While it is conventional to divide data into eight bit bytes, many microprocessors operate in a sixteen bit mode, where two eight bit data bytes are processed simultaneously. However, there are peripheral units that are only capable of processing a single eight bit byte of data. Also, some peripheral units, while capable of operating in a sixteen bit mode, may sometimes operate in an eight bit mode, for example, during initialization.
The sixteen bit data bus over which data is transferred between the microprocessor and the peripheral units is divided into a low eight bit byte portion and a high eight bit byte portion. When transferring data over the data bus, the data on the low eight bit byte portion is always considered to have an even address and the data on the high eight bit byte portion is always considered to have an odd address. However, a peripheral unit operating in an eight bit mode only recognizes the low eight bit byte portion of the data bus. Therefore, when a sixteen bit microprocessor transfers data to and from a peripheral unit operating in an eight bit mode, the microprocessor can only use even addresses so that the data is placed on the low eight bit byte portion of the data bus. It is apparent that such operation is unsatisfactory in that odd addresses could never be used and therefore the full capacity of the peripheral unit could not be realized.
In order to allow a sixteen bit microprocessor to satisfactorily transfer data between it and a peripheral unit operating in an eight bit mode, computer manufacturers have developed what is termed "byte-swap" hardware. There are two reasons why such byte swapping is necessary. First, if the sixteen bit microprocessor attempts to perform a sixteen bit access to or from an eight bit peripheral unit, the hardware must break the single access into two separate eight bit accesses, the first to the byte address corresponding to the word address of the access and the second to the next byte address. Secondly, an access to an odd byte address, whether it is a single eight bit access or half of a sixteen bit access broken into two eight bit accesses, must shift the data from the high byte portion of the data bus to the low byte portion of the data bus in the case of a write, or from the low byte portion of the data bus to the high byte portion of the data bus in the case of a read. This shift is necessary because the sixteen bit microprocessor transmits and receives data at odd addresses over the high byte portion of the data bus, while eight bit peripheral units contain only the low byte portion of the data bus. Without this shift, the odd address byte of data would be lost.
As can be imagined, the necessary byte-swap hardware is complex and expensive. It is therefore a primary object of the present invention to provide an arrangement whereby a sixteen bit microprocessor can perform the aforedescribed byte-swapping without the necessity for expensive and complex hardware.